R A D I X
Kanchan Bagh, Hyderabad - 58 info@radixmicrotech.com

Turret Position and Transmission Indicator

To replace the three systems configuration of ARJUN MARK ‘I’ Turret Position Transmitter and Indicator (TPTI) using Absolute Shaft Encoder has been developed. The system is intended to convert the existing analog system into digital system and introduces CAN Bus for ease of connectivity in the Mark II version of ARJUN Tanks.

Specifications:

FPGA Based
  • ANALOG to DIGITAL CONVERTER : Serial 1 MSPS 8-bit.
  • DIGITAL to ANALOG CONVERTER : Serial 8-bit.
  • Communication Interfaces : a) RS-232 b) CAN Bus c) RS-422
  • FPGA : Xilinx Spartan-3AN
  • Memory : 256Mb NOR Flash Memory
  • MUX : 16x1 MUX.
  • Environmental Qualification : EMI/EMC and ESS qualified.

Other Specifications can also be achieved depending on Customer Requirements.

Data Processing Unit

The Data Processing Unit FPGA based embedded system designed and developed for processing the raw information from the front end Receiver to a 128bit Signal Descriptor Word. The processed signal descriptor word is transmitted to host controller in 27.4ns on optical fiber link @ 3.125Gbps. The card is enclosed in a Conduction Cooled Mechanical enclosure specifically fabricated as per the customer requirement, meeting all the requirements of VITA 46 Standards.

Specifications:

Data-Processing-Unit
    FPGA :
  • XILINX VIRTEX-6 FPGA.
  • Memory :
  • 1) 1Gb DDR2 Memory..
  • 2) 256Mb NOR-FLASH Memory.
  • Communication
  • 1) 10/100/1000 Mbps Ethernet.
  • 2) 3.125Gbps Optical Fiber Links.
  • 3) RS-232.
  • Qualification
  • ESS, EMI/EMC Qualified.
    Digital I/Os :
  • >300 TTL/LVTTL.
  • Other Features
  • 1) Power good Indicator
  • 2) Temperature Sensor.
  • 3) +5V single supply voltage.
  • Qualification
  • ESS, EMI/EMC Qualified.

Other Specifications can also be achieved depending on Customer Requirements.

Receiver Processor Board

The Receiver processor unit accepts the pulse to pulse data (like Frequency, Pulse width, Amplitude, Direction of Arrival, time of Arrival etc.) measured by an ESM receiver and converts them into a time synchronous 128 bit data organized as 32bits x 4words. This board forms the interface between the receiver processor output and ESM processor input. The 32 bit x 4word data is interfaced to a high speed fiber optic cable (using a parallel to serial data converter) for onward transmission to an ESM processor. The maximum shadow time for transmitting the data for one pulse is <200ns (excluding the length of the fiber optic cable).

Specifications:

Receiver Processor Board
    FPGA :
  • XILINX VIRTEX-5 FPGA with TWO IBM PPC440 cores.
  • Memory :
  • 1) 1Gb DDR2 Memory..
  • 2) 256Mb NOR-FLASH Memory.
  • Communication
  • 1) 10/100/1000 Mbps Ethernet.
  • 2) 3.125Gbps Optical Fiber Links.
  • 3) RS-422.
  • 3) RS-232.
  • Qualification
  • ESS, EMI/EMC Qualified.
    Digital I/Os :
  • >500 TTL/LVTTL.
  • Other Features
  • 1) Power good Indicator
  • 2) Temperature Sensor.
  • 3) +5V single supply voltage.
  • Qualification
  • ESS, EMI/EMC Qualified.

Other Specifications can also be achieved depending on Customer Requirements.

Receiver Processor Board

The Receiver processor unit accepts the pulse to pulse data (like Frequency, Pulse width, Amplitude, Direction of Arrival, time of Arrival etc.) measured by an ESM receiver and converts them into a time synchronous 128 bit data organized as 32bits x 4words. This board forms the interface between the receiver processor output and ESM processor input. The 32 bit x 4word data is interfaced to a high speed fiber optic cable (using a parallel to serial data converter) for onward transmission to an ESM processor. The maximum shadow time for transmitting the data for one pulse is <200ns (excluding the length of the fiber optic cable).

Specifications:

Receiver Processor Board
    FPGA :
  • XILINX VIRTEX-5 FPGA with TWO IBM PPC440 cores.
  • Memory :
  • 1) 1Gb DDR2 Memory..
  • 2) 256Mb NOR-FLASH Memory.
  • Communication
  • 1) 10/100/1000 Mbps Ethernet.
  • 2) 3.125Gbps Optical Fiber Links.
  • 3) RS-422.
  • 3) RS-232.
    Digital I/Os :
  • >500 TTL/LVTTL.
  • Other Features
  • 1) Power good Indicator
  • 2) Temperature Sensor.
  • 3) +5V single supply voltage.
  • Qualification
  • ESS, EMI/EMC Qualified.

Other Specifications can also be achieved depending on Customer Requirements.

Automated Test-Jig for Avionic Interface Unit

The Automated Test-jig for Avionics unit is Virtex–5 FPGA based embedded system designed and developed for simultaneously testing four Avionic sub-systems with MIL-STD-1553 interfaces. The system is ported with Embedded Linux (Kernel 3.4), A multi-tasking algorithm has been developed to test the avionic sub-systems. The table top Automated Test-Jig for Avionics board is enclosed in a mechanical enclosure specifically fabricated asper the customer requirement to comply with full ESS specifications.

Specifications:

Automated Test-Jig for Avionic Interface
    FPGA :
  • XILINX VIRTEX-5 FPGA with TWO IBM PPC440 cores.
  • Memory :
  • 1) 1Gb DDR2 Memory..
  • 2) 4Mb NOR-FLASH Memory.
  • Communication
  • 1) 10/100/1000 Mbps Ethernet.
  • 2) MIL-STD-1553.
  • 3) RS-422.
  • 3) RS-232.
  • 3) USB.
    Digital I/Os :
  • >>500 TTL Lines Level Translated to LVTTL.
  • Other Features
  • 1) Digital I/Os.
  • 2) DAC
  • 3) ADC
  • 4) Power good Indicator,
  • 5) +28V single supply voltage.

Other Specifications can also be achieved depending on Customer Requirements.

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